In a first conventional method for erasing data stored in a non-volatile semiconductor memory such as an electrically erasable programmable read only memory (EEPROM), especially, a flash EEPROM, data stored in the whole memory cell array or one block divided therefrom which composes the non-volatile semiconductor memory fabricated on a semiconductor chip are erased electrically in one erasing operation. Such an erasing operation is carried out by applying a high voltage to a memory cell transistor composing the non-volatile semiconductor memory. One type of the memory cell transistor in which the erasing operation is carried out includes a source and a drain formed within the surface of a p-type semiconductor substrate with a predetermined distance, and a composite gate consisting of a first gate insulation layer, a floating gate electrode, a second gate insulation layer and a control gate electrode formed between the source and the drain on the p-type semiconductor substrate.
In operation of erasing data stored in the memory cell transistor, the source is applied with a high positive voltage on condition that the control gate electrode is fixed to the ground level and the drain is kept at a floating state. On these conditions, the electrons accumulated in the floating gate electrode are transferred to the source through the first gate insulation layer located between the floating gate electrode and the source by Fouel-Nordheim (F-N) tunnelling.
In a second conventional method for erasing data stored in a non-volatile semiconductor memory, one pulse of a high voltage is applied to a memory cell transistor. One type of the memory cell transistor in which the erasing operation is carried out includes p- type well region formed within the surface of an n-type semiconductor substrate, a source and a drain formed within the surface of the p-type well region with a predetermined distance, and a composite gate consisting of a first gate insulation layer, a floating gate electrode, a second gate insulation layer and a control gate electrode formed between the source and the drain on the p- type well region.
In operation of erasing data in the memory cell transistor, the p-type well region and the n-type semiconductor substrate are applied with one pulse of a high positive voltage on condition that the control gate electrode is fixed to the ground level and the source and drain are kept at a floating state. On these conditions, the electrons accumulated in the floating gate electrode are transferred to the p-type well region through the first gate insulation layer by F-N tunnelling.
The second conventional method for erasing data stored in a non-volatile semiconductor memory has been described on page 129 of 1990 Symposium on VLSI Technology Digest of Technical Papers, entitled "A NAND STRUCTURED CELL WITH A NEW PROGRAMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROM".
According to the fist and second conventional methods for erasing data stored in a non-volatile semiconductor memory, however, there are disadvantages as described below. In the first conventional method for erasing data stored in a non-volatile semiconductor memory, a deep depletion layer is generated in the surface of the source located below the floating gate electrode by applying such a high positive voltage, so that there is induced the inter-band tunnelling which causes the generation of holes therein. The holes thus generated are partly injected to the first gate insulation layer which is deteriorated thereby.
In the second conventional method for erasing data stored in a non-volatile semiconductor memory, other circuit elements fabricated in the p-type semiconductor substrate for activating the erasing operation of the memory cell transistor are isolated by corresponding p-type well regions which are fixed to the ground level to avoid electrical effects of the erasing operation of the memory cell transistor in the p-type well region to which a high positive voltage is applied. In this second conventional method for erasing data stored in a non-volatile semiconductor memory, the inter-band tunnel current does not flow during the erasing operation, so that the first gate insulation layer is not deteriorated thereby. However, the threshold voltage of the memory cell transistor tends to shift toward a negative region after the erasing operation is carried out, because many electrons are trapped in the whole layer of the first gate insulation layer under the floating gate electrode, and then released due to the self-field of the floating gate electrode. If the threshold voltage shifts toward the negative region after the erasing operation, the memory cell transistor may become at the depletion state which is a so called over-erasing state.